DocumentCode
165906
Title
Comparative analysis of 8 X 8 Bit Vedic and Booth Multiplier
Author
Garg, Shelly ; Garg, Shelly ; Sachdeva, Vipin
Author_Institution
Electron. & Commun., ITM Univ., Gurgaon, India
fYear
2014
fDate
24-27 Sept. 2014
Firstpage
2607
Lastpage
2610
Abstract
Speed and power consumption are one of the most important parameters to judge the performance of a computational method. In this paper, we compare two algorithms for 8 Bit multiplication namely Vedic Multiplication Algorithm and Booth algorithm. This paper aims in bringing to the fore the differences in compilation speeds and the chip area consumption of the two methodologies. The programming language used is Verilog and the synthesis has been done on Xilinx 14.5.
Keywords
digital arithmetic; Booth algorithm; Vedic multiplication algorithm; Vedic multiplier; Verilog; Xilinx 14.5; booth multiplier; chip area consumption; compilation speeds; programming language; word length 8 bit; Adders; Algorithm design and analysis; Delays; Educational institutions; Logic gates; Signal processing algorithms; Booth Multiplication; Vedic Multiplication; Verilog; Xilinx;
fLanguage
English
Publisher
ieee
Conference_Titel
Advances in Computing, Communications and Informatics (ICACCI, 2014 International Conference on
Conference_Location
New Delhi
Print_ISBN
978-1-4799-3078-4
Type
conf
DOI
10.1109/ICACCI.2014.6968224
Filename
6968224
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