Title :
A novel 0.25 μm CMOS technology for 6.82 μm2 6-Tr. SRAM cell with elevated trench isolation and line-and-space shaped gates (ETILS)
Author :
Nakabayashi, T. ; Uehara, T. ; Segawa, M. ; Ukeda, T. ; Yamanaka, M. ; Yamada, T. ; Arai, M. ; Yabu, T. ; Yamashita, K. ; Kobayashi, S. ; Murakami, T. ; Saeki, M. ; Okuyama, H. ; Kanda, A. ; Ogura, M.
Author_Institution :
Semicond. Res. Center, Matsushita Electr. Ind. Co. Ltd., Moriguchi, Japan
Abstract :
Miniaturization of SRAM cell size is a key issue for multi-media logic CMOS LSIs, such as DSP and MPEG2 decoders/encoders. Recently, several CMOS technologies realizing small cell size less than 10 μm 2 have been reported, while the previous work by M. Minami et al. (1995) achieved an even smaller cell size of 6.93 μm2, but this process required two-level local-interconnect. In this paper, a novel 0.25 μm CMOS technology is developed by an elevated trench isolation technology and line-and-space shaped gate formation (ETILS). This process allows the smallest cell size of 6.82 μm2 with simple single-level local-interconnect
Keywords :
CMOS memory circuits; SRAM chips; integrated circuit technology; isolation technology; 0.25 micron; CMOS technology; ETILS; SRAM cell; elevated trench isolation; line/space shaped gates; single-level local-interconnect; CMOS process; CMOS technology; Contact resistance; Electric variables; Electrodes; Etching; Lithography; MOSFET circuits; Random access memory; Threshold voltage;
Conference_Titel :
Electron Devices Meeting, 1995. IEDM '95., International
Conference_Location :
Washington, DC
Print_ISBN :
0-7803-2700-4
DOI :
10.1109/IEDM.1995.499388
