Floating Point Coprocessor for distributed array controllers

This paper describes a novel architecture of IEEE-754 compatible Floating Point Coprocessor (FPC) interfaced to an 8- bit microcontroller soft core for distributed array controller ASIC. FPC supports addition/subtraction, multiplication, division and comparison operations. FPC register bank is mapped as a shared dual port memory with micro-controller to minimize the overhead of data transfer. FPC contains 256×32-bit LUT for storage of trigonometric or user defined functions. LUTs and instruction memory are mapped as “stack” register with microcontroller, so it can be initialized by multiple “push” to a single Special Function Register (SFR). Space borne distributed array controller ASICs utilize 8 bit microcontroller cores due to their advantage in terms of low memory size, area and power consumption, but they are slow in floating point computations. This FPC enables real time floating point computations without the need of 32-bit microcontrollers. The FPC IP core has been implemented in VHDL and its performance has been compared for different cases. Simulation results shows that FPC gives 40× improvement in run time for distributed control applications.