DocumentCode :
1659181
Title :
A novel switch architecture for high-performance computing and signal processing networks
Author :
Sukhtankar, Satyen ; Hecht, Diana ; Rosen, Warren
Author_Institution :
Rydal R&D, PA, USA
fYear :
2004
Firstpage :
215
Lastpage :
222
Abstract :
This work describes low-latency switch architecture for high performance packet-switched networks. The switch architecture is a combination of input buffers capable of avoiding head-of-line blocking and an internal switch interconnect capable of allowing different input ports to access a single output port simultaneously. The switch was designed for the RapidIO protocol, but provides improved performance in other switched fabrics as well. OPNET Modeler was used to develop models of the proposed switch architecture and to evaluate the performance of the switch for three different network topologies. Models of two standard switch architectures were also developed and simulated for comparison.
Keywords :
packet switching; performance evaluation; protocols; OPNET Modeler; RapidIO protocol; head-of-line blocking; high performance packet-switched networks; high-performance computing; input buffers; internal switch interconnect; low-latency switch architecture; network topologies; performance evaluation; signal processing networks; Computer architecture; Computer networks; Delay; Fabrics; High performance computing; Network topology; Packet switching; Research and development; Signal processing; Switches;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Network Computing and Applications, 2004. (NCA 2004). Proceedings. Third IEEE International Symposium on
Print_ISBN :
0-7695-2242-4
Type :
conf
DOI :
10.1109/NCA.2004.1347780
Filename :
1347780
Link To Document :
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