Title :
A successive approximation A/D converter with 16 bit 200 kS/s in 0.6 μm CMOS using self calibration and low power techniques
Author :
Neubauer, Harald ; Desel, Thomas ; Hauer, Hans
Author_Institution :
Fraunhofer Inst. for Integrated Circuits, Erlangen, Germany
fDate :
6/23/1905 12:00:00 AM
Abstract :
A low power (6.8 mW) 5 V analog 2.7 V digital 16 bit 200 kS/s charge redistribution self calibrating successive approximation (SA) analog/digital converter (ADC) is presented. The device is implemented in a 0.6 μm CMOS technology with 2 mm2 active area. This multi purpose ADC macro is intended to be integrated with digital signal processing on ASICs. The SA principle permits input multiplexing and sampling at discrete times
Keywords :
CMOS integrated circuits; analogue-digital conversion; application specific integrated circuits; calibration; digital signal processing chips; integrated circuit design; integrated circuit measurement; low-power electronics; signal sampling; 0.6 micron; 16 bit; 2.7 V; 5 V; 6.8 mW; ASICs; CMOS ADC; CMOS technology; SA input multiplexing; digital signal processing; discrete time sampling; low power self calibrating successive approximation ADC; low power techniques; multi purpose ADC macro; self-calibration techniques; successive approximation A/D converter; Analog integrated circuits; CMOS analog integrated circuits; CMOS digital integrated circuits; CMOS integrated circuits; CMOS technology; Calibration; Capacitors; Energy consumption; Operational amplifiers; Power amplifiers;
Conference_Titel :
Electronics, Circuits and Systems, 2001. ICECS 2001. The 8th IEEE International Conference on
Print_ISBN :
0-7803-7057-0
DOI :
10.1109/ICECS.2001.957609
