Enhancing lithography for 1.0 micron and larger designs

The market for integrated circuits with feature sizes above 1.0 μm continues to play a tremendous role in the overall IC market. These circuits are built in highly competitive environments. In order to successfully compete, manufacturing costs must be optimized. A limited number of new wafer fabs are being built for >1.0 μm designs; most additional capacity in this area comes from facilities that are upgraded. This paper evaluates the cost of ownership of the exposure tools that serve this market. Several costs are evaluated, including labor, maintenance, facilities, reticles/masks and capital. Issues unique to existing facilities, such as continuing production while changing equipment, are also addressed. Technology considerations, including yield and extendability, are discussed. Results indicate that lithography systems can be designed that are highly cost effective and efficiently implemented in an upgrade environment