Title :
A high-performance architectural design for motion estimation in MPEG-4
Author :
Guhagarkar, Nikhil R. ; Shaik, Rafi Ahamed
Author_Institution :
Dept. of Electron. & Electr. Eng., Indian Inst. of Technol. Guwahati, Guwahati, India
Abstract :
The key to high performance of MPEG-4 video compression lies in an efficient reduction of spatial and temporal redundancy. The main idea of inter prediction techniques is quick checking of the entire search area with efficient matching criterion viz. sum of absolute difference to eliminate the impossible or least matched candidates, followed by finer selection among the potentially best matched candidates. The macroblock with least SAD value will decide the motion vector. Due to object-based nature of MPEG-4, new SAD design with efficient computational ability, less area and less power in 0.18μm CMOS technology and operating frequency of 1.508GHz is proposed in the following paper.
Keywords :
CMOS integrated circuits; motion estimation; video coding; CMOS technology; MPEG-4; SAD design; frequency 1.508 GHz; high-performance architectural design; motion estimation; motion vector; size 0.18 mum; video compression; Arrays; Motion estimation; Signal processing algorithms; Transform coding; Very large scale integration; SAD; VLSI architecture; block matching; integer motion estimation; macro block; motion estimation; systolic array;
Conference_Titel :
Communications (NCC), 2012 National Conference on
Conference_Location :
Kharagpur
Print_ISBN :
978-1-4673-0815-1
DOI :
10.1109/NCC.2012.6176795