On the construction of frame length specific LDPC codes for next generation low power communication

In this paper, a new method is proposed for constructing frame length specific LDPC codes which consume low power in encoding and decoding processes. A seed matrix is used and extended to form the parity check matrix having frame lengths divisible by 32 and 64. This method can be used to construct the LDPC codes with frame lengths divisible by even higher power of 2. The memory requirements for encoding and decoding processes of the proposed codes is discussed in this paper. For typical configuration the memory requirements to store the parity check matrix for the encoding and decoding processes are ≤ 1.04% and ≤ 33.33% respectively in comparison to the memory requirements in the traditional encoding and decoding processes. Hence consume low power in their encoding and decoding processes. The different configurations of the proposed codes are simulated and it is found that the codes give desirable error performance over AWGN channel.