Design of a cycle-efficient 64b/32b integer divider using a table-sharing method

Author

Chua-Chin Wang ; Lee, Po-Ming ; Jun-Jie Wang ; Huang, Chenn Jung

Author_Institution

Dept. of Electr. Eng., Nat. Sun Yat-Sen Univ., Kaohsiung, Taiwan

Volume

2

fYear

2001

fDate

6/23/1905 12:00:00 AM

Firstpage

921

Abstract

In new generations of microprocessors, the superscalar architecture is widely adopted to increase the number of instructions executed in one cycle. The division instruction among all of the instructions needs more cycles than the rest, e.g., addition and multiplication. It then, makes division instruction an important CPI (cycles per instruction) figure for modern microprocessors. In this paper, a radix 16/8/4/2 divider is proposed which uses a variety of techniques, including operand scaling, table partitioning, and table folding, to increase performance without the cost of increasing complexity

Keywords

digital arithmetic; dividing circuits; iterative methods; logic partitioning; microprocessor chips; 32 bit; 64 bit; addition; cycle-efficient 64b/32b integer divider; cycles per instruction figure; division instruction; microprocessors; multiplication; operand scaling; radix 16/8/4/2 divider; superscalar architecture; table folding; table partitioning; table-sharing method; Computer science; Computer science education; Costs; Councils; Educational institutions; Hardware; Microprocessors; Partitioning algorithms; Table lookup;

fLanguage

English

Publisher

ieee

Conference_Titel

Electronics, Circuits and Systems, 2001. ICECS 2001. The 8th IEEE International Conference on

Print_ISBN

0-7803-7057-0

Type

conf

DOI

10.1109/ICECS.2001.957623

Filename

957623