Stand-by low-power architecture in a 3 V-only 2-bit/cell 64-Mbit flash memory

Author

Micheloni, Rino ; Motta, Ilaria ; Khouri, Osama ; Torelli, Guido

Author_Institution

Memory Product Group, STMicroelectronics, Milan, Italy

Volume

2

fYear

2001

fDate

6/23/1905 12:00:00 AM

Firstpage

929

Abstract

Presents a low-power stand-by management circuit designed for a 64-Mbit, 2-bit/cell 3 V-only Flash memory device. An auxiliary charge pump operated by a noncontinuous clock acts as a low-power recharge circuit during stand-by, thus keeping the word-line voltage generation structures charged to a suitable level. A dedicated circuitry minimizes word-line voltage transients during recovery from stand-by. The access time when entering read mode from stand-by is equal to the asynchronous access time in normal operation (120 ns), even though the stand-by current consumption of the whole memory chip is limited to less than 40 μA

Keywords

flash memories; low-power electronics; memory architecture; transients; 120 ns; 3 V; 40 muA; 64 Mbit; access time; asynchronous access time; auxiliary charge pump; flash memory; noncontinuous clock; read mode; recharge circuit; stand-by current consumption; stand-by low-power architecture; word-line voltage generation structures; word-line voltage transients; Charge pumps; Circuits; Clocks; Electronic mail; Flash memory; Memory management; Nonvolatile memory; Parasitic capacitance; Regulators; Voltage control;

fLanguage

English

Publisher

ieee

Conference_Titel

Electronics, Circuits and Systems, 2001. ICECS 2001. The 8th IEEE International Conference on

Print_ISBN

0-7803-7057-0

Type

conf

DOI

10.1109/ICECS.2001.957625

Filename

957625