Optimized programming of multilevel flash EEPROMs

Author

Versari, Roberto ; Esseni, David ; Falavigna, Gianluca ; Lanzoni, Massimo ; Ricco, Bruno

Author_Institution

DEIS, Bologna Univ., Italy

Volume

2

fYear

2001

fDate

6/23/1905 12:00:00 AM

Firstpage

945

Abstract

The trade-off between speed and dispersion of programmed threshold voltages is investigated in 0.25 μm flash memory technology. It is shown that ramped gate programming provides tighter distributions of programmed threshold voltages than its conventional box-waveform counterpart, allowing a larger number of bits per second to be written. In particular, at low programming speed, ramped gate programming is shown to allow four level schemes without program and verify operations, with a program bandwidth potentially approaching 30 Mbits/s in the conventional one-bit-per-cell scheme (and correspondingly higher values in the multi-level case). Instead, sixteen level schemes without program and verify do not seem practically feasible

Keywords

PLD programming; flash memories; integrated circuit testing; integrated memory circuits; microprogramming; optimisation; 0.25 micron; 30 Mbit/s; box-waveform programming; flash memory technology; multilevel flash EEPROMs; multilevel schemes; one-bit-per-cell scheme; optimized programming; program bandwidth; program/verify operations; programmed threshold voltages; programming speed; ramped gate programming; Appropriate technology; Bandwidth; Bit rate; Circuit testing; EPROM; Flash memory; Nonvolatile memory; Power generation; Threshold voltage; Voltage control;

fLanguage

English

Publisher

ieee

Conference_Titel

Electronics, Circuits and Systems, 2001. ICECS 2001. The 8th IEEE International Conference on

Print_ISBN

0-7803-7057-0

Type

conf

DOI

10.1109/ICECS.2001.957629

Filename

957629