Modeling of a three phase SPWM multilevel VSI with low THD using Matlab/Simulink

Researches done based on basic inverter topologies show that multilevel inverters (MLIs) have many advantages, such as low power dissipation on power switches, low dv/dt ratios, low harmonic and low electromagnetic interference (EMI) outputs. The most common MLI topologies have been studied to define the most appropriate structure for Sinusoidal Pulse Width Modulation (SPWM) strategy. It is seen that cascaded H-bridges are the most convenient solution. The cascaded H-bridge cells have been constituted by IGBT semiconductors, and switched by the proposed 24-channel SPWM modulator to obtain 5-level output at the back-end of the 3-phase voltage source inverter (VSI). A modified 24 channels SPWM modulator that reduces output harmonics has been presented in this study to switch cascaded H-bridge cells of multilevel VSI. The designed multilevel VSI has a THD_i ratio around at 0.1% and a strong switching bandwidth up to 40 kHz, owing to its well designed modulator. The modeling operations are also examined in Matlab/Simulink to obtain a practical solution for three-phase SPWM modulator. Various design steps and configurations have been considered to model the modulator and the success of modulator has been tested under several conditions such as increased modulation indexes and switching frequencies.