Title :
A channel decoder implemented by CMOS analog circuits in digital communication system
Author :
Yang, Shuhui ; Li, Xuehua ; Wang, Yafei
Author_Institution :
Coll. of Photoelectricity Inf. & Commun. Eng., Beijing Inf. Sci. & Technol. Univ., Beijing
Abstract :
To realize low power channel decoder in digital communication system, basing on the a-posteriori probability algorithm, the paper fabricates an analog probability decoder of trellis code by using CMOS analog circuits. The decoding performance is given. When the SNR is over 4.8 dB, for 950 KHz input signal, the analog decoderpsilas BER is zero. If the input signal is 6 MHz, the BER will be about 10-4.The highest speed of the decoder can be up to 20 MHz. Simulation results also show that the analog decoder decreases at least one order of magnitude in power consumption and chip area at the same rate compared with the digital decoder. The design method is also suitable for implementing the analog decoders of Turbo code and LDPC code.
Keywords :
CMOS analogue integrated circuits; digital communication; error statistics; parity check codes; trellis codes; turbo codes; BER; CMOS analog circuits; LDPC code; a-posteriori probability; analog decoder; chip area; digital communication system; low power channel decoder; power consumption; trellis code; turbo code; Analog circuits; Bit error rate; CMOS analog integrated circuits; CMOS digital integrated circuits; Convolutional codes; Decoding; Design methodology; Digital communication; Energy consumption; Turbo codes;
Conference_Titel :
Signal Processing, 2008. ICSP 2008. 9th International Conference on
Conference_Location :
Beijing
Print_ISBN :
978-1-4244-2178-7
Electronic_ISBN :
978-1-4244-2179-4
DOI :
10.1109/ICOSP.2008.4697489
