Title :
A multiple bits error correction method based on cyclic redundancy check codes
Author :
Zhang, Yanbin ; Yuan, Qi
Author_Institution :
Coll. of Inf. Technol., Beijing Inst. of Technol., Beijing
Abstract :
A method which links the judge and data check is provided. The method realizes the ability of multiple bits error correction using cyclic redundancy check codes. The error correction principle and realization method are described in detail. The key parameters design of the method is analyzed. The simulation results show that the multiple bits error correction method can improve the bit error rate and packet error rate effectively.
Keywords :
cyclic redundancy check codes; error correction codes; error statistics; bit error rate; cyclic redundancy check codes; data check; judge check; multiple bits error correction method; packet error rate; Cyclic redundancy check; Cyclic redundancy check codes; Data communication; Design methodology; Educational institutions; Error correction; Error correction codes; Error probability; Information technology; Polynomials; cyclic redundancy check; error correction; frame error probability; multiple bits error;
Conference_Titel :
Signal Processing, 2008. ICSP 2008. 9th International Conference on
Conference_Location :
Beijing
Print_ISBN :
978-1-4244-2178-7
Electronic_ISBN :
978-1-4244-2179-4
DOI :
10.1109/ICOSP.2008.4697490
