The Hardware Realization of the Bicubic Interpolation Enlargement Algorithm Based on FPGA

Author

Zhang, Yunshan ; Li, Yuhui ; Zhen, Jie ; Li, Jionghao ; Xie, Ran

Author_Institution

Yunnan Adm. Coll., Yunnan Provincial Comm. Sch. of the CPC, Kunming, China

fYear

2010

Firstpage

277

Lastpage

281

Abstract

There is an improvement to the Bicubic interpolation enlargement algorithm based on the hardware parallel processing in this article. Search table method used in this paper has avoided massive cubic and the floating numbers multiply operation. It reduces the computation load greatly. Convolution operation in tow directions, level and vertical, of the 4x4 picture element matrix on FPGA has been realized by LPM. The Bicubic interpolation enlargement algorithm is completely based on the hardware parallel characteristic to realize. This method has the superiority in the computation speed and occupies on the resources.

Keywords

convolution; field programmable gate arrays; image enhancement; image resolution; interpolation; Bicubic interpolation enlargement algorithm; FPGA; convolution operation; floating numbers; hardware parallel processing; hardware realization; picture element matrix; search table method; Convolution; Field programmable gate arrays; Hardware; Interpolation; Mathematical model; Pixel; Software algorithms; Bicubic interpolation enlargement; FPGA; convolution operation; parallel processing; picture element matrix;

fLanguage

English

Publisher

ieee

Conference_Titel

Information Processing (ISIP), 2010 Third International Symposium on

Conference_Location

Qingdao

Print_ISBN

978-1-4244-8627-4

Type

conf

DOI

10.1109/ISIP.2010.82

Filename

5669050