Efficient system level cache architecture for multimedia SoC

A typical multimedia SoC consists of hardware components for image capture & processing, video compression and de-compression, computer vision, graphics and display processing. Each of these components access and compete for the limited bandwidth available in the shared external DDR memory. The traditional solution of using cache is not suitable for multimedia traffic. In this paper, we propose a novel cache architecture which is beneficial for multimedia traffic in terms of DDR bandwidth savings and latency reduction. The proposed cache architecture uses qualifier based splitter, multiple fully associative configurable features cache and an arbiter. The proposed cache architecture is evaluated using architectural model. The paper also proposes newer applications of this cache architecture as an infinite circular buffer for data buffer sharing across hardware components. The simulation results show 50% improvement in DDR bandwidth for video decoder traffic.