On-line calibration for non-linearity reduction of delay-locked delay-lines

Author

Baronti, F. ; Fanucci, L. ; Lunardini, D. ; Roncella, R. ; Saletti, R.

Author_Institution

Dipt. di Ingegneria dell´´Informazione: Elettronica, Informatica, Telecomunicazioni, Pisa Univ., Italy

Volume

2

fYear

2001

fDate

6/23/1905 12:00:00 AM

Firstpage

1001

Abstract

A reduction of the non-linearity of a CMOS all-digital shunt-capacitor delay-line is achieved by performing an on-line statistical test of the line and correcting the individual cell delay mismatch according to the test results. A fully digital cell controller efficiently implementing the calibration procedure has been realized. Simulation results show the feasibility of the technique and the substantial reduction of the nonlinearity down to values lower then 1%

Keywords

CMOS digital integrated circuits; calibration; delay lines; delay lock loops; integrated circuit testing; CMOS shunt-capacitor delay-line; DLL delay lines; DLL nonlinearity testing; cell delay mismatch correction; delay-locked loop delay-lines; digital cell controller; digital shunt-capacitor DLL; nonlinearity reduction; online calibration; online statistical test; Calibration; Circuits; Clocks; Delay effects; Delay lines; Digital control; Feedback loop; Linearity; Performance evaluation; Testing;

fLanguage

English

Publisher

ieee

Conference_Titel

Electronics, Circuits and Systems, 2001. ICECS 2001. The 8th IEEE International Conference on

Print_ISBN

0-7803-7057-0

Type

conf

DOI

10.1109/ICECS.2001.957642

Filename

957642