Design of power efficient SPI interface

The paper discusses the design of an SPI interface based on the specifications mentioned in the SPI block guide V03.06 by Motorola. The present design incorporates additional power down mode - stop mode for power optimization and the standard design was modified by using clock gating technique for additional power reduction. The shift registers are replaced by double buffer registers to prevent the loss of data due to overflow. Using clock gating in the design has reduced the power of the shift register by 13%. Verilog is used for coding and I-Sim (Xilinx) is used to verify the design performance.