Design and optimization of a low jitter clock-conversion PLL for SONET/SDH optical transmitters

A robust clock-conversion PLL is presented for use in optical transmitters. The alignment-free PLL has a fully integrated loop-filter, rail-to-rail high-ohmic-input V/I-converter and a double-integrator oscillator which leads to small chip-area. The PLL frequency response is optimized for minimisation of the jitter of the output signal. All critical building blocks are designed for 2.4 V, in order to allow stacking of a voltage stabiliser with good power supply rejection ratio. The 155/622 MHz PLL is realized in BiCMOS technology with 18 GHz cut-off frequency. The PLL is evaluated under temperature conditions ranging from -40°C to 85°C and found SONET/SDH compliant. Maximum transmit jitter is 4.4 mUI rms. Active chip area is 1.65 mm². The dissipation is 65 mW with a 3.0 V power supply voltage