Title :
Design and optimization of a low jitter clock-conversion PLL for SONET/SDH optical transmitters
Author :
Van der Tang, Johan D. ; Vaucher, Cicero S.
Author_Institution :
Philips Res. Lab., Eindhoven, Netherlands
fDate :
6/23/1905 12:00:00 AM
Abstract :
A robust clock-conversion PLL is presented for use in optical transmitters. The alignment-free PLL has a fully integrated loop-filter, rail-to-rail high-ohmic-input V/I-converter and a double-integrator oscillator which leads to small chip-area. The PLL frequency response is optimized for minimisation of the jitter of the output signal. All critical building blocks are designed for 2.4 V, in order to allow stacking of a voltage stabiliser with good power supply rejection ratio. The 155/622 MHz PLL is realized in BiCMOS technology with 18 GHz cut-off frequency. The PLL is evaluated under temperature conditions ranging from -40°C to 85°C and found SONET/SDH compliant. Maximum transmit jitter is 4.4 mUI rms. Active chip area is 1.65 mm2. The dissipation is 65 mW with a 3.0 V power supply voltage
Keywords :
BiCMOS integrated circuits; SONET; UHF integrated circuits; circuit optimisation; digital communication; jitter; optical transmitters; phase locked loops; synchronisation; synchronous digital hierarchy; timing; -40 to 85 degC; 155 MHz; 18 GHz; 2.4 V; 3 V; 622 MHz; 65 mW; BiCMOS technology; ITU SONET/SDH standard compliance; PLL frequency response; SONET/SDH optical transmitters; VCO design; alignment-free PLL; double-integrator oscillator; fully integrated loop-filter; high-ohmic-input V/I converter; low jitter PLL; rail-to-rail V/I converter; robust clock-conversion PLL; voltage stabiliser; Clocks; Design optimization; Frequency response; Jitter; Optical transmitters; Oscillators; Phase locked loops; Power supplies; Robustness; Voltage;
Conference_Titel :
Electronics, Circuits and Systems, 2001. ICECS 2001. The 8th IEEE International Conference on
Print_ISBN :
0-7803-7057-0
DOI :
10.1109/ICECS.2001.957655
