DocumentCode :
1660474
Title :
Monitoring methodology for TID damaging of SDRAM devices based on retention time analysis
Author :
Bertazzoni, S. ; Di Giovenale, D. ; Salmeri, M. ; Mencattini, A. ; Salsano, A. ; Florean, M.
Author_Institution :
Dept. of Electron. Eng., Univ. di Roma, Italy
fYear :
2004
Firstpage :
106
Lastpage :
110
Abstract :
Total ionizing dose (TID) is a potential problem for solid state devices exposed to ionizing radiation. An important parameter to define is the level of TID the device can tolerate. This value is very useful in order to predict its operative life time in a radiation environment. In this paper an online monitoring method to measure the degradation of synchronous dynamic RAM (SDRAM) commercial off the shelf (COTS) devices due to TID is proposed. The method is based on the measurement of the bit retention time, that is the time the information is retained in a memory cell without refresh. This approach is based on the observation that on same die, a dispersion of the devices´ characteristics exists. So, the device degradation will appear in a more evident way in those memory cells having worst electrical characteristics. For this reason, there is a gradual increment of the number of memory cells that do not maintain their initialization value with the increment of the absorbed dose. The proposed method is useful to monitor the real level of degradation of a SDRAM device in order to optimize maintenance activity and graceful performance degradation techniques. SDRAM devices are used as a TID radiation defector to monitor the real dose absorbed by itself, and thus by the whole apparatus. The method is based on functional test that a SDRAM controller can easily perform on empty memory blocks without requiring dedicated hardware. This paper presents the experimental setup and the results of a preliminary TID test with a 60Co gamma ray source on SDRAM COTS to validate the method.
Keywords :
DRAM chips; SRAM chips; condition monitoring; gamma-ray effects; integrated circuit reliability; integrated circuit testing; Co; Co gamma ray source; SDRAM COTS; SDRAM controller memory blocks; SDRAM devices; TID damage monitoring methodology; TID radiation detector; TID tolerance level; absorbed dose; bit retention time; cell initialization value; commercial off the shelf devices; device degradation; electrical characteristics; functional test; ionizing radiations; maintenance activity; memory cell; online monitoring method; operative life time; radiation environment; retention time analysis; synchronous dynamic RAM; total ionizing dose; DRAM chips; Degradation; Electric variables; Ionizing radiation; Monitoring; Random access memory; SDRAM; Solid state circuits; Testing; Time measurement;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Defect and Fault Tolerance in VLSI Systems, 2004. DFT 2004. Proceedings. 19th IEEE International Symposium on
ISSN :
1550-5774
Print_ISBN :
0-7695-2241-6
Type :
conf
DOI :
10.1109/DFTVS.2004.1347830
Filename :
1347830
Link To Document :
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