Title :
A difference detector PFD for low jitter PLL
Author :
Cheng, Kuo-Hsing ; Yao, Tse-Hua ; Jiang, Shu-Yu ; Yang, Wei-Bin
Author_Institution :
Dept. of Electr. Eng., Tamkang Univ., Taipei Hsien, Taiwan
fDate :
6/23/1905 12:00:00 AM
Abstract :
For high speed and low jitter PLL application, a new phase frequency detector (PFD) with difference detector is proposed. Because the proposed difference detector PFD (dd-PFD) doesn´t have any feedback path in phase frequency detector circuit, it can be operated up to 1.6 GHz. Furthermore, with difference detector, the dd-PFD has three states, so it will not have phase errors and jitter problems. The dead zone of dd-PFD is 16 ps. The proposed PFD is designed using 0.35 μm CMOS technology at 3.3 V power supply
Keywords :
CMOS analogue integrated circuits; high-speed integrated circuits; phase detectors; phase locked loops; timing jitter; 0 to 1.6 GHz; 0.35 micron; 3.3 V; CMOS technology; dd-PFD; dead zone; high speed PLL; low jitter PLL; phase frequency detector; Circuits; Clocks; Delay; Filters; Jitter; Phase detection; Phase frequency detector; Phase locked loops; Signal generators; Voltage-controlled oscillators;
Conference_Titel :
Electronics, Circuits and Systems, 2001. ICECS 2001. The 8th IEEE International Conference on
Print_ISBN :
0-7803-7057-0
DOI :
10.1109/ICECS.2001.957660
