Designs for reducing test time of distributed small embedded SRAMs

Author

Wang, Baosheng ; Wu, Yuejian ; Ivanov, André

Author_Institution

Dept. of Electr. & Comput. Eng., British Columbia Univ., Vancouver, BC, Canada

fYear

2004

Firstpage

120

Lastpage

128

Abstract

This paper proposes a test architecture aimed at reducing test time of distributed small embedded SRAMs (e-SRAMs). This architecture improves the one proposed in (W. B. Jone et al, Proc. 17th IEEE VLSI Test Symp., p.246- 251, 1999 and also IEEE Transact. VLSI Syst., vol.10, no.4, p.512-515, 2002). The improvements are mainly two-fold. On one hand, the testing of time-consuming data retention faults (DRFs), that is neglected by the previously proposed test architecture, is now considered and performed via a DFT technique referred to as the "no write recovery test mode (XWRTM)". On the other hand, a parallel local response analyzer (LRA), instead of a serial response analyzer, is used to reduce the test time of these distributed small e-SRAMs. Results from our evaluations show that the proposed test architecture can achieve a better defect coverage and test time compared to those obtained previously, with a negligible area cost.

Keywords

SRAM chips; design for testability; integrated circuit testing; logic testing; DFT technique; DRF; LRA; SRAM test time reduction; SoC; XWRTM; data retention faults; defect coverage; distributed small embedded SRAM; e-SRAM; no write recovery test mode; parallel local response analyzer; test architecture; Built-in self-test; Circuit faults; Circuit testing; Computer architecture; Pattern analysis; Performance evaluation; Random access memory; Routing; Sequential analysis; System-on-a-chip;

fLanguage

English

Publisher

ieee

Conference_Titel

Defect and Fault Tolerance in VLSI Systems, 2004. DFT 2004. Proceedings. 19th IEEE International Symposium on

ISSN

1550-5774

Print_ISBN

0-7695-2241-6

Type

conf

DOI

10.1109/DFTVS.2004.1347832

Filename

1347832