• DocumentCode
    1660710
  • Title

    Modeling and analysis of crosstalk coupling effect on the victim interconnect using the ABCD network model

  • Author

    Palit, Ajoy K. ; Meyer, V. ; Anheier, W. ; Schloeffel, Juergen

  • Author_Institution
    ITEM, Bremen Univ., Germany
  • fYear
    2004
  • Firstpage
    174
  • Lastpage
    182
  • Abstract
    After order reduction, the crosstalk model is utilized for the analysis of crosstalk coupling effects on the victim´s output signal. Various timing issues related to signal waveform such as, delay time, overshoot and undershoot occurrence time etc., that in effect help to ensure the desired signal integrity (SI) and performance reliability of the SoCs, can be estimated analytically using the reduced order crosstalk model. It has been observed that the crosstalk coupling effect introduces a delay in the victim´s output signal which can be significant enough, or even unacceptable, if many aggressors simultaneously couple energy to the victim line, or the line spacing between the aggressor and victim is reduced due to under-etching ,or even, the length of the victim interconnect is increased because of improper layout/routing. Influences of other interconnect parasitics on the victim´s output signal can also be tested using the same model. Simulation results obtained with our reduced order model is found to be quite good and comparable to the accuracy of PSPICE simulation.
  • Keywords
    coupled circuits; integrated circuit interconnections; integrated circuit modelling; integrated circuit reliability; interference (signal); reduced order systems; system-on-chip; ABCD network model; SoC performance reliability; aggressor line crosstalk coupling effect modeling; delay time; interconnect parasitics; layout effects; line spacing; overshoot; reduced order crosstalk model; routing effects; signal integrity; undershoot occurrence time; victim interconnect; Crosstalk; Delay effects; Delay estimation; Performance analysis; Propagation delay; Reduced order systems; Routing; Signal analysis; Testing; Timing;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Defect and Fault Tolerance in VLSI Systems, 2004. DFT 2004. Proceedings. 19th IEEE International Symposium on
  • ISSN
    1550-5774
  • Print_ISBN
    0-7695-2241-6
  • Type

    conf

  • DOI
    10.1109/DFTVS.2004.1347838
  • Filename
    1347838