Title :
Reducing fault latency in concurrent on-line testing by using checking functions over internal lines
Author :
Pomeranz, Irith ; Reddy, Sudhakar M.
Author_Institution :
Sch. of Electr. & Comput. Eng., Purdue Univ., West Lafayette, IN, USA
Abstract :
We describe a method to reduce the fault latency, i.e., the time it takes to detect a fault after it occurs, during concurrent on-line testing. A high fault latency can negatively affect the fault coverage in various ways. The fault latency is reduced by using what we call checking functions. A checking function cfi expresses the function of a line gi in the circuit as a function of one or more other lines. During concurrent on-line testing, the value of gi is compared to the value of cfi. A mismatch indicates the presence of a fault. The advantage of checking functions is that they only use lines that already exist in the circuit. We demonstrate that benchmark circuits have large numbers of checking functions to choose from. We also demonstrate the increase in fault coverage and the reductions in fault detection times possible by using checking functions.
Keywords :
fault simulation; logic testing; concurrent on-line testing; fault coverage; fault detection time reduction; fault latency reduction; fault simulation; internal line checking functions; Benchmark testing; Circuit faults; Circuit testing; Cities and towns; Delay; Electrical fault detection; Fault detection; Hardware; Logic circuits; Logic testing;
Conference_Titel :
Defect and Fault Tolerance in VLSI Systems, 2004. DFT 2004. Proceedings. 19th IEEE International Symposium on
Print_ISBN :
0-7695-2241-6
DOI :
10.1109/DFTVS.2004.1347839