Title :
Mixed loopback BiST for RF digital transceivers
Author :
Dàbrowski, Jerzy ; Bayon, Javier Gonzalez
Author_Institution :
Dept. of Electr. Eng., Linkoping Univ., Sweden
Abstract :
In this paper we analyze the performance of a mixed built-in-self-test (BiST) for RF IC digital transceivers, where a baseband processor can be used both as a test pattern generator and response analyzer. The test is oriented at spot defects in a transceiver front-end. Estimates for noise, signal power and nonlinear distortions such as EVM (or SER), gain and IP3, respectively, are considered the test responses. Limitations of these tests are investigated with respect to the test path properties, the strength of defects and circuit tolerances. The IP3 test complements the EVM (SER) and gain tests for some spot defects. The analysis is verified by simulation of a functional-level RF transceiver model implemented in Matlab™.
Keywords :
automatic test pattern generation; built-in self test; circuit simulation; fault location; integrated circuit modelling; integrated circuit noise; integrated circuit testing; nonlinear distortion; radiofrequency integrated circuits; transceivers; EVM tests; IP3; Matlab functional-level RF transceiver model simulation; RF IC digital transceivers; SER; baseband processor; circuit tolerances; defect strength; gain test; mixed built-in-self-test; mixed loopback BiST; noise estimates; nonlinear distortion estimates; response analyzer; signal power estimates; spot defects; test limitations; test path properties; test pattern generator; test responses; transceiver front-end; Baseband; Circuit testing; Digital integrated circuits; Integrated circuit noise; Pattern analysis; Performance analysis; Radio frequency; Radiofrequency integrated circuits; Test pattern generators; Transceivers;
Conference_Titel :
Defect and Fault Tolerance in VLSI Systems, 2004. DFT 2004. Proceedings. 19th IEEE International Symposium on
Print_ISBN :
0-7695-2241-6
DOI :
10.1109/DFTVS.2004.1347843
