Title :
M×N Booth encoded multiplier generator using optimized Wallace trees
Author :
Fadavi-Ardekani, Jalil
Author_Institution :
AT&T Bell Lab., Allentown, PA, USA
Abstract :
The architecture and the design method for an M-×- N Booth-encoded parallel-multiplier generator are discussed. An algorithm for reducing the delay inside the branches of the Wallace tree section is presented and explained. The final stage of adding two (N +M-1)-bit numbers is done by an optimal carry-select adder stage. An algorithm for optimal partitioning of the (N+M -1)-bit adder is also presented
Keywords :
adders; digital arithmetic; M*N Booth encoded multiplier generator; delay; optimal carry-select adder stage; optimal partitioning; optimized Wallace trees; parallel-multiplier generator; Adders; Circuits; Delay; Design methodology; Digital signal processing; Encoding; Flow graphs; Partitioning algorithms; Production; Signal processing algorithms;
Conference_Titel :
Computer Design: VLSI in Computers and Processors, 1992. ICCD '92. Proceedings, IEEE 1992 International Conference on
Conference_Location :
Cambridge, MA
Print_ISBN :
0-8186-3110-4
DOI :
10.1109/ICCD.1992.276195
