Routable technology mapping for LUT FPGAs

Author

Bhat, Narasimha B. ; Hill, Dwight D.

Author_Institution

Dept. of EECS, California Univ., Berkeley, CA, USA

fYear

1992

Firstpage

95

Lastpage

98

Abstract

A routing-driven technology mapper for lookup-table, (LUT)-based field-programmable gate arrays (FPGAs) is presented. The approach is based on performing mapping aimed at routing feasibility. For an FPGA of given size (number of LUTs), the logic being implemented is distributed in such a manner that the total wire length is minimized and the routing resources are not overutilized. Simulated annealing is used to perform mapping, placement, and global routing in tandem. The algorithm can handle both combinational and sequential logic circuits, and has been implemented for combinational circuits. Experiments on MCNC benchmark circuits show encouraging results

Keywords

circuit layout CAD; combinatorial circuits; logic arrays; table lookup; MCNC benchmark circuits; combinational logic circuits; field-programmable gate arrays; global routing; lookup-table; routing feasibility; routing-driven technology mapper; sequential logic circuits; simulated annealing; total wire length; Circuit simulation; Circuit synthesis; Combinational circuits; Delay; Field programmable gate arrays; Logic design; Routing; Sequential circuits; Simulated annealing; Table lookup;

fLanguage

English

Publisher

ieee

Conference_Titel

Computer Design: VLSI in Computers and Processors, 1992. ICCD '92. Proceedings, IEEE 1992 International Conference on

Conference_Location

Cambridge, MA

Print_ISBN

0-8186-3110-4

Type

conf

DOI

10.1109/ICCD.1992.276199

Filename

276199