DocumentCode
1661048
Title
High throughput pipelined architecture for fast 2-D 4×4 forward integer transform of H.264
Author
Mukherjee, R. ; Prasad, W. Hari ; Dheeraj, P. ; Chakrabarti, I. ; Sengupta, S.
Author_Institution
Electron. & Electr. Commun. Eng., Indian Inst. of Technol. Kharagpur, Kharagpur, India
fYear
2012
Firstpage
1
Lastpage
5
Abstract
The H.264 standard uses integer transform block in its encoder. In this paper, a pipelined architecture of fast 2-D forward integer transform is proposed. For video compression applications such as Television Studio Broadcast or Surveillance Videos, where throughput is of prime importance for real-time encoding, we propose an efficient realization of the forward integer transform unit. Using Xilinx Virtex-5 technology, the proposed architecture gives an excellent throughput of 5383 Mpixels/sec, where the critical path delay is 2.97 ns and the maximum operating frequency is of 336 MHz.
Keywords
data compression; field programmable gate arrays; transforms; video coding; H.264 standard; Xilinx Virtex-5 technology; fast 2D forward integer transform; frequency 336 MHz; high-throughput pipelined architecture; integer transform block; real-time encoding; surveillance videos; television studio broadcast; time 2.97 ns; video compression applications; Adders; Application specific integrated circuits; Computer architecture; Field programmable gate arrays; Streaming media; Throughput; Transforms; Conditional Sum Adder; H.264 encoder; Integer Transform; pipelined architecture;
fLanguage
English
Publisher
ieee
Conference_Titel
Communications (NCC), 2012 National Conference on
Conference_Location
Kharagpur
Print_ISBN
978-1-4673-0815-1
Type
conf
DOI
10.1109/NCC.2012.6176853
Filename
6176853
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