Title :
First level hold: a novel low-overhead delay fault testing technique
Author :
Bhunia, S. ; Mahmoodi, H. ; Raychowdhury, A. ; Roy, K.
Author_Institution :
Electr. & Comput. Eng., Purdue Univ., West Lafayette, IN, USA
Abstract :
This paper presents a novel delay fault testing technique, which can be used as an alternative to the enhanced scan based delay fault testing, with significantly less design overhead. Instead of using an extra latch as in the enhanced scan method, we propose using supply gating at the first level of logic gates to hold the state of the combinational circuit. Experimental results on a set of ISCAS89 benchmarks show an average reduction of 27% in area overhead with an average improvement of 62% in delay overhead and 87% in power overhead during normal mode of operation, compared to the enhanced scan implementation.
Keywords :
combinational circuits; delays; fault location; integrated circuit design; integrated circuit testing; logic design; logic gates; logic testing; ISCAS89 benchmarks; average area overhead reduction; combinational circuit state; delay overhead; design overhead; enhanced scan based delay fault testing; first level hold low-overhead delay fault testing technique; logic gates; normal mode operation; power overhead; supply gating; Circuit faults; Circuit testing; Combinational circuits; Delay; Design engineering; Inverters; Latches; Logic gates; Logic testing; Timing;
Conference_Titel :
Defect and Fault Tolerance in VLSI Systems, 2004. DFT 2004. Proceedings. 19th IEEE International Symposium on
Print_ISBN :
0-7695-2241-6
DOI :
10.1109/DFTVS.2004.1347854
