Title :
VLSI design of modulo adders/subtractors
Author_Institution :
Texas Tech. Univ., Lubbock, TX, USA
Abstract :
Elegant implementation of modulo adders are presented. A design suitable for small moduli is given first, and then, by using the divide and conquer approach, a design for large moduli is derived. The designs are such that modulo subtraction can also be performed on the same hardware. The designs are suitable for high-speed digital parallel processing. The propagation delay of a modulo-64 adder realized using this design is 12 ns
Keywords :
VLSI; adders; delays; 12 ns; VLSI design; digital parallel processing; divide and conquer approach; modulo adders/subtractors; modulo subtraction; modulo-64 adder; propagation delay; Adders; Arithmetic; Delay; Dynamic range; Hardware; Logic design; Parallel processing; Signal processing; Very large scale integration; Zirconium;
Conference_Titel :
Computer Design: VLSI in Computers and Processors, 1992. ICCD '92. Proceedings, IEEE 1992 International Conference on
Conference_Location :
Cambridge, MA
Print_ISBN :
0-8186-3110-4
DOI :
10.1109/ICCD.1992.276205
