VLSI design of modulo adders/subtractors

Elegant implementation of modulo adders are presented. A design suitable for small moduli is given first, and then, by using the divide and conquer approach, a design for large moduli is derived. The designs are such that modulo subtraction can also be performed on the same hardware. The designs are suitable for high-speed digital parallel processing. The propagation delay of a modulo-64 adder realized using this design is 12 ns