Nonvolatile repair caches repair embedded SRAM and new nonvolatile memories

Author

Fong, John Y. ; Acklin, Randy ; Roscher, John ; Li, Feng ; Laird, Cindy ; Pietrzyk, Cezary

Author_Institution

Texas Instrum. Inc., Dallas, TX, USA

fYear

2004

Firstpage

347

Lastpage

355

Abstract

Nonvolatile repair caches require less area than traditional row, column, or block redundancy schemes, to repair random defective memory cells in deep submicron embedded SRAMs and new nonvolatile memories such as FeRAM, MRAM, and OUM. Small memories with few defects can be repaired efficiently in real time by the direct mapped nonvolatile repair cache whereas large memories with many defects can be repaired more effectively and in real time by the N way set associative repair cache. An 8 way set associative repair cache was implemented in the Texas Instruments-Agilent Technologies 64 Mbit FeRAM chip.

Keywords

SRAM chips; cache storage; content-addressable storage; ferroelectric storage; integrated circuit technology; integrated circuit yield; magnetic storage; maintenance engineering; 64 Mbit; FeRAM; MRAM; N way set associative repair cache; OUM; direct mapped nonvolatile repair cache; embedded SRAM repair; memory defects; nonvolatile memory repair; nonvolatile repair caches; random defective memory cells; redundancy schemes; CMOS process; Copper; Etching; Fault tolerant systems; Ferroelectric films; Instruments; Nonvolatile memory; Random access memory; Redundancy; Very large scale integration;

fLanguage

English

Publisher

ieee

Conference_Titel

Defect and Fault Tolerance in VLSI Systems, 2004. DFT 2004. Proceedings. 19th IEEE International Symposium on

ISSN

1550-5774

Print_ISBN

0-7695-2241-6

Type

conf

DOI

10.1109/DFTVS.2004.1347859

Filename

1347859