Automatic methodology for placing the guard rings into chip layout to prevent latchup in CMOS IC´s

Author

Ker, Ming-Dou ; Jiang, Hsin-Chin ; Peng, Jeng-Jie ; Shieh, Tzay-Luen

Author_Institution

Integrated Circuits & Syst. Lab., Nat. Chiao-Tung, Taiwan

Volume

1

fYear

2001

fDate

6/23/1905 12:00:00 AM

Firstpage

113

Abstract

A program methodology is proposed to automatically place the guard rings in the chip layout to improve latchup immunity of the CMOS ICs. The additional guard rings between the I/O cells and the internal circuits had been practically proven to significantly increase the latchup immunity of CMOS ICs. Therefore, the layout spacing from the I/O cells to the internal circuits can be reduced to a reasonable distance to save the total chip size. In this paper, a "guard ring automation" program to realize the additional guard rings in the layout is proposed to make the layout more automatically and accurately

Keywords

CMOS integrated circuits; circuit layout CAD; integrated circuit layout; protection; CMOS IC; CMOS IC latchup prevention; I/O cells; automatic methodology; chip layout; guard ring automation program; guard ring placement; guard rings; internal circuits; latchup immunity; layout spacing; program methodology; total chip size; CMOS analog integrated circuits; CMOS integrated circuits; CMOS process; CMOS technology; Equivalent circuits; Integrated circuit layout; Laboratories; MOS devices; Pins; Variable structure systems;

fLanguage

English

Publisher

ieee

Conference_Titel

Electronics, Circuits and Systems, 2001. ICECS 2001. The 8th IEEE International Conference on

Print_ISBN

0-7803-7057-0

Type

conf

DOI

10.1109/ICECS.2001.957690

Filename

957690