Performance analysis of alternative adder cell structures using clocked and non-clocked logic styles at 45nm technology

In this paper, the performance analysis of alternative full adder cell structures using various clocked and non-clocked logic styles were implemented for deep-submicron CMOS technology. Various clocked and non-clocked logic styles are used for the implementation of CMOS full-adder circuits. In this paper, the circuits considered for performance comparison are: non-clocked logic styles namely Static, CPL, DPL, SR-CPL, modified SR-CPL, modified DPL and clocked logic styles namely Dynamic logic, FTL, and CD logic. All these full-adder cell structures are compared based on power and delay analysis. The design of adder cells is carried-out in Cadence Virtuoso Analog Design Environment at 45nm CMOS process technology and simulated using Spectre simulator.