Accurate estimation of soft error rate (SER) in VLSI circuits

Trends in CMOS technology have resulted in circuits with higher soft error rate (SER), making it imperative to accurately estimate the SER of VLSI circuits. In this paper a comparative study is presented between the Q_crit method and the simulation method for estimating the circuit level SER. It is shown that for small circuits with uniformly distributed output values (e.g. flip-flop, binary counter), both methods provide similar estimates for SER. However, for other circuits the Q_crit-based method provides SER estimates significantly different from the results of the simulation method. Errors of up to 34% have been observed for a microprocessor scoreboard circuit. This is due to the fact that the Q_crit method assumes that each node in the circuit is equally likely to be 0 or 1. The Q_crit method can also miss out logical masking within the circuit. Finally, a feasible method based on Monte-Carlo simulation is presented to estimate chip level SER in terms of failure in time (FIT) rate.