DocumentCode :
1661374
Title :
Exploiting an I-IP for in-field SoC test
Author :
Bernardi, P. ; Rebaudengo, M. ; Reorda, M. Sonza
Author_Institution :
Politecnico di Torino, Italy
fYear :
2004
Firstpage :
404
Lastpage :
412
Abstract :
Today´s complex system-on-chip integrated circuits include a wide variety of functional IPs whose correct manufacturing must be guaranteed by IC producers. Infrastructure IPs are increasingly often inserted to achieve this purpose; such blocks, explicitly designed for test, are coupled with functional IPs both to obtain yield improvement during the manufacturing process and to perform volume production test. In this paper, a new test control schema based on the use of an infrastructure IP (I-IP) is proposed for the test on-site of SoCs. The proposed in-field test strategy is based on the ability of a single I-IP to periodically monitor the behavior of the system by reusing the test structures introduced for manufacturing test. The feasibility of this approach has been proved for SoCs including microprocessors and memories equipped with P1500 compliant solutions. Experimental results highlight the advantages in term of reusability and scalability, low impact on system availability and reduced area overhead.
Keywords :
industrial property; integrated circuit design; integrated circuit testing; integrated memory circuits; microprocessor chips; production testing; system-on-chip; I-IP; P1500 compliant solutions; area overhead; functional IP manufacturing; in-field SoC test; in-field test strategy; infrastructure IP blocks; manufacturing test; memories; microprocessors; on-site SoC test; reusability; scalability; system availability; system-on-chip integrated circuits; test control schema; test structure reuse; volume production test; yield improvement; Circuit testing; Coupling circuits; Integrated circuit manufacture; Integrated circuit yield; Manufacturing processes; Monitoring; Performance evaluation; Production; System testing; System-on-a-chip;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Defect and Fault Tolerance in VLSI Systems, 2004. DFT 2004. Proceedings. 19th IEEE International Symposium on
ISSN :
1550-5774
Print_ISBN :
0-7695-2241-6
Type :
conf
DOI :
10.1109/DFTVS.2004.1347865
Filename :
1347865
Link To Document :
بازگشت