Title :
Alpha architecture: Hardware implementation and software programming implications
Author_Institution :
Digital Equipment Corp., Hudson, MA, USA
Abstract :
A description is given of Alpha, a 64-bit RISC architecture designed with emphasis on clock speed, multiple instruction issues and multiple processors. The author discusses byte manipulation, arithmetic traps, shared memory, the Privileged Architecture Library (PALcode), and Alpha´s attractiveness for compiling a large variety of programming languages
Keywords :
reduced instruction set computing; 64 bit; 64-bit RISC architecture; Alpha architecture; Hardware implementation; PALcode; Privileged Architecture Library; arithmetic traps; byte manipulation; clock speed; multiple instruction issues; multiple processors; shared memory; software programming; Arithmetic; Buildings; Computer architecture; Delay; Hardware; Logic; Pipeline processing; Read-write memory; Reduced instruction set computing; Registers;
Conference_Titel :
Computer Design: VLSI in Computers and Processors, 1992. ICCD '92. Proceedings, IEEE 1992 International Conference on
Conference_Location :
Cambridge, MA
Print_ISBN :
0-8186-3110-4
DOI :
10.1109/ICCD.1992.276216
