DocumentCode
1661476
Title
Reliability modeling and assurance of clockless wave pipeline
Author
Feng, Tao ; Park, Nahea
Author_Institution
Dept. of Comput. Sci., Oklahoma State Univ., Stillwater, OK, USA
fYear
2004
Firstpage
442
Lastpage
450
Abstract
This paper presents theoretical yet practical methodologies to model, assure and optimize the reliability of clockless wave pipeline. Clockless wave pipeline is a cutting-edge and innovative technology as an alternative to traditional pipeline, and a promising computing model towards ultra-high throughput and speed. The basic computational components of such clockless wave pipeline are data waves in association with request signals and switches. The key to the success of clockless wave pipeline is how to coordinate and ensure the processing of datawaves throughout the pipeline in association with the request signals without relying on any intermediate access points under clocked-control. Due to the complication of clockless operations, an efficient and effective method to model and analyze the confidence level (referred to as reliability or yield) of clockless operations of wave pipeline is exigently demanded, but has not yet been adequately addressed, in an integrated level such as datawaves in association with request signals, leaving this as a challenge. In this regard, out-of-orchestration between datawaves and request signals, referred to as datawave fault, is the major concern in assuring and optimizing the reliability of the system. This paper specifically addresses and resolves: extensive and practical clockless-induced datawave-fault modeling; assurance and optimization; clockless-oriented fault tolerant design methods. The proposed methods will establish a sound and adequate theoretical foundation for development of innovative yet practical test/diagnosis/fault-tolerant design methods in early design stage of clockless wave pipeline.
Keywords
circuit analysis computing; fault simulation; fault tolerant computing; logic testing; microprocessor chips; pipeline processing; reliability; clocked-control; clockless wave pipeline; clockless-induced datawave-fault modeling; clockless-oriented fault tolerant design methods; computational components; computing model; confidence level; datawave processing; early design stage; intermediate access points; reliability assurance; reliability modeling; request signals; ultra-high speed; ultra-high throughput; wave pipeline clockless operations; Clocks; Design methodology; Fault tolerance; Optimization methods; Pipelines; Reliability theory; Signal analysis; Signal processing; Switches; Throughput;
fLanguage
English
Publisher
ieee
Conference_Titel
Defect and Fault Tolerance in VLSI Systems, 2004. DFT 2004. Proceedings. 19th IEEE International Symposium on
ISSN
1550-5774
Print_ISBN
0-7695-2241-6
Type
conf
DOI
10.1109/DFTVS.2004.1347869
Filename
1347869
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