The design space of ultra-low energy asymmetric cryptography

The energy cost of asymmetric cryptography, a vital component of modern secure communications, inhibits its wide spread adoption within the ultra-low energy regimes such as Implantable Medical Devices (IMDs), Wireless Sensor Networks (WSNs), and Radio Frequency Identification tags (RFIDs). Consequently, a gamut of hardware/software acceleration techniques exists to alleviate this energy burden. In this paper, we explore this design space, estimating the energy consumption for three levels of acceleration across the commercial security spectrum. First we examine an efficient baseline architecture centered around a pipelined RISC processor. We then include simple, yet beneficial instruction set extensions to our microarchitecture and evaluate the improvement in terms of energy per operation compared to baseline. Finally, we introduce a novel, dedicated accelerator to our microarchitecture and measure the energy per operation against the baseline and the ISA extensions. For ISA extensions, we show between 1.28 to 1.41 factor improvement in energy efficiency over baseline, while for full acceleration we demonstrate a 4.36 to 6.45 factor improvement.