Title :
RTL design verification by making use of datapath information
Author :
Fujita, Masahiro
Author_Institution :
Fujitsu Labs. Ltd., Kawasaki, Japan
Abstract :
An RTL (register level) design verification method that first separates a given design into a datapath and a control circuit and fully utilizes information obtained from the datapath when verifying the control circuit is presented. The method has been successfully applied to the verification of a real 20K-gate chip that performs interface control between processors and networks in a parallel machine. So far, one fifth of the functions of the chip have been verified, in less than a 1 min on SPARC2
Keywords :
formal verification; logic CAD; 20K-gate chip; RTL design verification; SPARC2; control circuit; datapath; datapath information; interface control; parallel machine; register transfer level; Circuits; Delay estimation; Design methodology; Formal verification; Hardware; Laboratories; Logic; Parallel machines; Process control; Registers;
Conference_Titel :
Computer Design: VLSI in Computers and Processors, 1992. ICCD '92. Proceedings, IEEE 1992 International Conference on
Conference_Location :
Cambridge, MA
Print_ISBN :
0-8186-3110-4
DOI :
10.1109/ICCD.1992.276219
