DocumentCode
166162
Title
PriME: A parallel and distributed simulator for thousand-core chips
Author
Yaosheng Fu ; Wentzlaff, David
Author_Institution
Princeton Univ., Princeton, NJ, USA
fYear
2014
fDate
23-25 March 2014
Firstpage
116
Lastpage
125
Abstract
Modern processors are integrating an increasing number of cores, which brings new design challenges. However, mainstream architectural simulators primarily focus on unicore or multicore systems with small core counts. In order to simulate emerging manycore architectures, more simulators designed for thousand-core systems are needed. In this paper, we introduce the Princeton Manycore Executor (PriME), a parallelized, MPI-based, x86 manycore simulator. The primary goal of PriME is to provide high performance simulation for manycore architectures, allowing fast exploration of architectural ideas including cache hierarchies, coherence protocols and NoCs in thousand-core systems. PriME supports multi-threaded workloads as well as multi-programmed workloads. Furthermore, it parallelizes the simulation of multi-threaded workloads inside of a host machine and parallelizes the simulation of multi-programmed workloads across multiple host machines by utilizing MPI to communicate between different simulator modules. By using two levels of parallelization (within a host machine and across host machines), PriME can improve simulation performance which is especially useful when simulating thousands of cores. Prime is especially adept at executing simulations which have large memory requirements as previous simulators which use multiple machines are unable to simulate more memory than is available in any single host machine. We demonstrate PriME simulating 2000+ core machines and show near-linear scaling on up to 108 host processors split across 9 machines. Finally we validate PriME against a real-world 40-core machine and show the average error to be 12%.
Keywords
digital simulation; message passing; microprocessor chips; multi-threading; multiprocessing systems; multiprogramming; parallel architectures; 40-core machine; MPI-based manycore simulator; NoCs; PriME; Princeton manycore executor; architectural simulators; cache hierarchies; coherence protocols; distributed simulator; host processors; manycore architectures; multiple host machines; multiprogrammed workloads; multithreaded workloads; near-linear scaling; parallel simulator; thousand-core chips; thousand-core systems; x86 manycore simulator; Coherence; Instruction sets; Message systems; Multicore processing; Protocols;
fLanguage
English
Publisher
ieee
Conference_Titel
Performance Analysis of Systems and Software (ISPASS), 2014 IEEE International Symposium on
Conference_Location
Monterey, CA
Print_ISBN
978-1-4799-3604-5
Type
conf
DOI
10.1109/ISPASS.2014.6844467
Filename
6844467
Link To Document