A tool for automatic generation of BISTed and transparent BISTed RAMs

An efficient BIST architecture for RAMs that is based on M. Marinescu´s (1982) algorithm is presented. This architecture considers the different levels of hierarchy of the algorithm and uses a block to implement each level of this hierarchy. Efficient implementations for these blocks are given. A transparent BIST technique, i.e., a BIST technique that preserves the initial contents of the RAM, is also presented, and an efficient transparent BIST architecture for RAMs is proposed. A tool allowing the automatic generation of BISTed and transparent BISTed RAMs is given. This generator is developed around the CADENCE CAD tools and uses the ES2 SOLO2030 standard cell library (CMOS 1.2 μm)