FPGA leakage power reduction using clb-clustering technique

FPGAs with supply voltage programmability have been proposed recently to reduce FPGA power. In this paper, we propose CLB-clustering design technique that employs V_DD programmable and power gating methods to reduce leakage in standby mode. Compared to the conventional V_DD-programmable architecture, our architecture reduces the leakage power by - 32.78 dB with 2.32% more area.