Title :
Multirate digital squarer architectures
Author :
Fengqi Yu ; Willson, Alan N., Jr.
Author_Institution :
Integrated Circuits & Syst. Lab., California Univ., Los Angeles, CA, USA
fDate :
6/23/1905 12:00:00 AM
Abstract :
By using multirate signal processing, we propose interleaved and pipelined architectures for digital squarers. The hardware implementation of the proposed architectures and their complexity are discussed at the gate level. In comparison to a recently proposed divide-and-conquer squarer architecture, and for the same throughput, our squarer´s hardware complexity is approximately 15% less for a 16-bit squarer, and 23% less for a 32-bit squarer
Keywords :
digital signal processing chips; divide and conquer methods; parallel architectures; pipeline processing; 16 bit; 32 bit; divide-and-conquer architecture; hardware complexity; hardware implementation; interleaved architectures; multirate signal processing; pipelined architectures; Computer architecture; Delay; Digital integrated circuits; Digital signal processing; Hardware; Image coding; Laboratories; Signal processing algorithms; USA Councils; Vector quantization;
Conference_Titel :
Electronics, Circuits and Systems, 2001. ICECS 2001. The 8th IEEE International Conference on
Print_ISBN :
0-7803-7057-0
DOI :
10.1109/ICECS.2001.957709
