• DocumentCode
    1661769
  • Title

    32nm x86 OS-compliant PC on-chip with dual-core Atom® processor and RF WiFi transceiver

  • Author

    Lakdawala, Hasnain ; Schaecher, Mark ; Fu, Chang-tsung ; Limaye, Rahul ; Duster, Jon ; Tan, Yulin ; Balankutty, Ajay ; Alpman, Erkan ; Lee, Chun ; Suzuki, Satoshi ; Carlton, Brent ; Kim, Hyung Seok ; Verhelst, Marian ; Pellerano, Stefano ; Kim, Tong ; Sri

  • Author_Institution
    Intel, Hillsboro, OR, USA
  • fYear
    2012
  • Firstpage
    62
  • Lastpage
    64
  • Abstract
    Embedded PC applications are growing, driven by their cost, performance and software compatibility. The SoC described in this work is a unique device designed for rapid integration and customization for specific market segments. A rich multi-source IP eco-system consisting of standardized interfaces, modular and configurable building blocks, enables automation and fast execution to deliver a broad range of targeted solutions. Integrating high-performance digital circuits with analog and RF circuits on a leading edge process enables our SoC architecture to increase the level of integration, performance and reduce the cost of the platform. WiFi has remained an external PC component due to the challenges of managing system noise from the digital circuits. This paper presents an integrated standard x86 OS compliant, dual-core ATOM® processor-based SoC, including the RF WiFi to drive down platform cost. Key enabling features are: (a) a 32nm RF process with HV transistors and RF passives; (b) an on-chip interconnect fabric for modularity; (c) a clock generator with SSC to reduce substrate noise injection and EMI; (d) voltage regulators for power management and rail reduction; (e) an 802.11b/g RF WiFi transceiver with integrated LNA, PA, T/R switch and BIST/calibration engine.
  • Keywords
    calibration; clocks; electromagnetic interference; low noise amplifiers; microprocessor chips; power amplifiers; power aware computing; radio transceivers; system-on-chip; wireless LAN; 802.11b/g RF WiFi transceiver; BIST/calibration engine; EMI; HV transistor; LNA; PA; RF circuit; SoC architecture; T/R switch; analog circuit; clock generator; configurable building block; cost reduction; dual-core Atom processor; embedded PC application; external PC component; high-performance digital circuit; modular building block; multisource IP eco-system; on-chip interconnect fabric; power management; rail reduction; size 32 nm; software compatibility; standardized interface; substrate noise injection; system noise management; voltage regulator; x86 OS-compliant PC on-chip; CMOS integrated circuits; Clocks; IEEE 802.11 Standards; Program processors; Radio frequency; System-on-a-chip; Transceivers;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Solid-State Circuits Conference Digest of Technical Papers (ISSCC), 2012 IEEE International
  • Conference_Location
    San Francisco, CA
  • ISSN
    0193-6530
  • Print_ISBN
    978-1-4673-0376-7
  • Type

    conf

  • DOI
    10.1109/ISSCC.2012.6176879
  • Filename
    6176879