A single latch, high speed double-edge triggered flip-flop (DETFF)

Author

Johnson, Troy A. ; Kourtev, Ivan S.

Author_Institution

Dept. of Electr. Eng., Purdue Univ., West Lafayette, IN, USA

Volume

1

fYear

2001

fDate

6/23/1905 12:00:00 AM

Firstpage

189

Abstract

This paper describes an original circuit design of a static CMOS double-edge triggered flip-flop (DETFF). Double. edge triggered (DET) flip-flops are bistable flip-flop circuits in which data is latched at either edge of the clock signal. Using such flip-flops permits the rate of data processing to be preserved while using lower clock frequency (as compared to a circuit with single-edge triggered flip-flops). Therefore, power consumption in DETFF based circuits may be reduced. The proposed flip-flop design has fewer transistors than other published static CMOS DETFFs. The described circuit structure is laid out in a 0.5 μm process. Circuit simulations using Hspice demonstrate that the flip-flop is logically correct and functions as expected. Furthermore, the proposed design rates favorably when compared to existing static CMOS DETFF circuits

Keywords

CMOS logic circuits; flip-flops; high-speed integrated circuits; logic design; low-power electronics; 0.5 micron; bistable flip-flop circuits; clock frequency; double-edge triggered flip-flop; high speed flip-flop; power consumption reduction; single latch flip-flop; static CMOS flip-flop; Buildings; CMOS technology; Circuit synthesis; Clocks; Data processing; Energy consumption; Flip-flops; Frequency; Latches; Multiplexing;

fLanguage

English

Publisher

ieee

Conference_Titel

Electronics, Circuits and Systems, 2001. ICECS 2001. The 8th IEEE International Conference on

Print_ISBN

0-7803-7057-0

Type

conf

DOI

10.1109/ICECS.2001.957712

Filename

957712