• DocumentCode
    1661828
  • Title

    Protocol verification as a hardware design aid

  • Author

    Dill, David L. ; Drexler, Andreas J. ; Hu, Alan J. ; Yang, C. Han

  • Author_Institution
    Comput. Syst. Lab., Stanford Univ., CA, USA
  • fYear
    1992
  • Firstpage
    522
  • Lastpage
    525
  • Abstract
    The role of automatic formal protocol verification in hardware design is considered. Principles that maximize the benefits of protocol verification while minimizing the labor and computation required are identified. A novel protocol description language and verifier (both called Murφ) are described, along with experiences in applying them to two industrial protocols that were developed as part of hardware designs
  • Keywords
    formal verification; protocols; Mur phi; automatic formal protocol verification; computation; hardware design aid; protocol description language; Automata; Communication switching; Delay; Formal verification; Hardware; Logic; Out of order; Protocols; Switches; System recovery;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Computer Design: VLSI in Computers and Processors, 1992. ICCD '92. Proceedings, IEEE 1992 International Conference on
  • Conference_Location
    Cambridge, MA
  • Print_ISBN
    0-8186-3110-4
  • Type

    conf

  • DOI
    10.1109/ICCD.1992.276232
  • Filename
    276232
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=1661828