Synthesis on multiplexer-based FPGA using binary decision diagrams

Author

Besson, T. ; Bouzouzou, H. ; Crastes, M. ; Floricica, I. ; Saucier, G.

Author_Institution

Inst. Nat. Polytech. de Grenoble, France

fYear

1992

Firstpage

163

Lastpage

167

Abstract

Synthesis methods are presented for multiplexer-based field-programmable gate arrays, (FPGAs) based on binary decision diagrams (BDDs) for speed optimization, and reduced ordered binary decision diagrams (ROBDDs) for area optimization. A direct mapping is performed on the two types of binary decision diagrams. Practical results are given for an exhaustive list of benchmarks. The results show a big improvement compared to library based approaches

Keywords

logic arrays; logic design; optimisation; area optimization; benchmarks; binary decision diagrams; direct mapping; field-programmable gate arrays; logic synthesis; multiplexer-based FPGA; speed optimization; Application specific integrated circuits; Binary decision diagrams; Boolean functions; Data structures; Field programmable gate arrays; Libraries; Multiplexing; Optimization methods; Prototypes;

fLanguage

English

Publisher

ieee

Conference_Titel

Computer Design: VLSI in Computers and Processors, 1992. ICCD '92. Proceedings, IEEE 1992 International Conference on

Conference_Location

Cambridge, MA

Print_ISBN

0-8186-3110-4

Type

conf

DOI

10.1109/ICCD.1992.276241

Filename

276241

Link To Document

https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=1662001