DocumentCode
1662063
Title
An efficient twin-precision multiplier
Author
Själander, Magnus ; Eriksson, Henrik ; Larsson-Edefors, Per
Author_Institution
Dept. of Comput. Eng., Chalmers Univ. of Technol., Goteborg, Sweden
fYear
2004
Firstpage
30
Lastpage
33
Abstract
We present a twin-precision multiplier that in normal operation mode efficiently performs N-b multiplications. For applications where the demand on precision is relaxed, the multiplier can perform N/2-b multiplications while expending only a fraction of the energy of a conventional N-b multiplier. For applications with high demands on throughput, the multiplier is capable of performing two independent N/2-b multiplications in parallel. A comparison between two signed 16-b multipliers, where both perform single 8-b multiplications, shows that the twin-precision multiplier has 72% lower power dissipation and 15% higher speed than the conventional one, while only requiring 8% more transistors.
Keywords
low-power electronics; multiplying circuits; N-b multiplications; N-b multiplier; N/2-b multiplications; power dissipation; transistors; twin precision multiplier; Application software; Bit rate; Computer architecture; Delay; Instruction sets; Logic arrays; Power dissipation; Power engineering and energy; Throughput; Very large scale integration;
fLanguage
English
Publisher
ieee
Conference_Titel
Computer Design: VLSI in Computers and Processors, 2004. ICCD 2004. Proceedings. IEEE International Conference on
ISSN
1063-6404
Print_ISBN
0-7695-2231-9
Type
conf
DOI
10.1109/ICCD.2004.1347894
Filename
1347894
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