Low Power Multiplier using Dynamic Voltage and Frequency Scaling (DVFS)

In the recent years, the main concern of VLSI Engineers is on the power reduction techniques. In this paper, Dynamic Voltage Frequency Scaling (DVFS) for reducing power using Virtex 5 FPGA Kit along with XPower Estimator tool is used. In proposed DVFS technique, multiplication and addition are performed at different frequencies. Using sequential multiplier, practical analysis has been carried out. Its power is simulated without DVFS and further simulated the result with DVFS. Analyzing this result it is found that, power has been reduced drastically. The simulation results shows that 54.53% of total power and 25% of dynamic power is reduced using this approach as compared to non DVFS approach.