DocumentCode :
1662306
Title :
Asynchronous scan-latch controller for low area overhead DFT
Author :
Tsukisaka, Masayuki ; Imai, Masashi ; Nanya, Takashi
Author_Institution :
Res. Center for Adv. Sci. & Technol., Tokyo Univ., Japan
fYear :
2004
Firstpage :
66
Lastpage :
71
Abstract :
This paper introduces a new scan control technique to realize low area overhead of scan-latches. Single transparent-latch is popularly used for register of high-throughput datapaths. For the scan-test of those kind of circuits, each transparent-latch is replaced with scan-latch. Conventional scan-latch cells controlled by synchronous signals consist of L1 latch and additional L2 latch, both of which function as master latch and slave latch respectively in scan mode. Apparently, additional L2 latch may result in area overhead. In order to avoid the area impact of such an additional L2 latch, we propose new timing methodology employing asynchronous control technique asP* protocol, and introduce asynchronous controlled scan-paths whose scan-latch employs only L1 latch. We evaluate the operation speed with HSPICE simulations and see they are practical. We also suggest DFT structure with our suggested asynchronous scan-paths, which is suitable for conventional synchronous test systems.
Keywords :
SPICE; asynchronous circuits; design for testability; flip-flops; logic testing; shift registers; DFT; HSPICE simulation; asP protocol; asynchronous scan latch controller; asynchronous symmetric pulse persistent protocol; scan testing; shift registers; transparent latch; Application specific processors; Circuit simulation; Circuit testing; Clocks; Design for testability; Latches; Master-slave; Protocols; Shift registers; Timing;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Computer Design: VLSI in Computers and Processors, 2004. ICCD 2004. Proceedings. IEEE International Conference on
ISSN :
1063-6404
Print_ISBN :
0-7695-2231-9
Type :
conf
DOI :
10.1109/ICCD.2004.1347901
Filename :
1347901
Link To Document :
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